The present invention relates generally to integrated circuits (ICs), and more specifically to output buffers operable in a slew rate control mode or non slew rate control mode.
Digital ICs use output buffers to drive an external load. Output buffers are designed to provide enough current to drive a maximum permissible load level since the size of the load is usually unknown. This is typically accomplished by providing the output buffer with an output transistor large enough to drive the maximum permissible load or a number of smaller transistors coupled in parallel to drive the maximum permissible load.
As IC technologies continue to advance, the speed of IC has significantly increased, i.e. the time in which the output of a circuit responds to an input. Increasing speed has resulted in faster rise and fall times of the output voltage and abrupt transitions of output current. One problem is encountered when the conventional output buffers are quickly turned on or off. Since the currents are so large, fast switching of the conventional buffers can induce noise spikes on the power, ground and data buses, thereby causing data errors, latch-up and other problems in the digital electronic circuitry. This problem can be reduced by a technique known as slew rate control.
Slew rate is defined as the rate of output transition in volts per unit time. Conventional digital output buffers with a slew rate control scheme often use RPO resistors in series with the PGATE and NGATE drivers to reduce the abruptness of the transition of state, thereby reducing the noise. However, RPO resistors for the buffer are not ideal as additional masks have to be used for fabricating the RPO resistors. The additional masks increase the costs of the buffer. Furthermore, the design of the buffer with RPO resistors is not flexible, as the masks need to be revised when the buffer is redesigned to operate in a non-slew rate control mode. Finally, the RPO resistors are not an ideal slew rate control scheme and often cause the buffer to generate a crossbar current and consume excessive power.
As such, what is needed is an output buffer that can operate in both the slew rate control mode and the non-slew rate control mode for optimizing its performance and power efficiency.